1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device, and in particular, to an AG-AND type (assist gate-AND type) flash memory where floating gates and assist gates are alternately arranged.
2. Description of the Background Art
In recent years, demand in terms of specification on increased capacity in data storage flash memories, for example, increased capacity in memory cards together with the increase in the number of pixels of digital cameras has been very high. AG-AND type flash memories have been developed as one type of such data storage flash memories. In an AG-AND type flash memory, floating gates and assist gates are alternately arranged, and an intense inversion layer is formed as a lower layer by applying an electric field to an assist gate, so that this inversion layer is used as a bit line (see, for example, H. Kurata et al., 2004 Symposium on VLSI Circuits Digest of Technical Papers, pp. 72-73 (Non-Patent Document 1)).
FIG. 32 is a block diagram showing a major portion of one bank in such an AG-AND type flash memory. In FIG. 32, this bank is provided with a memory array MA, a sense latch SL and an X decoder XD. Memory array MA includes N strings ST0 to ST(N−1) (here, N is a natural number). Global bit lines GBL are arranged in such a manner as to cross N strings ST0 to ST(N−1). Global bit lines GBL are upper bit lines which are shared by all strings ST0 to ST(N−1), and have a function of connecting sense latch SL and memory cell transistors.
Sense latch SL controls whether or not write-in is carried out in a memory cell transistor by conveying necessary information along global bit line GBL in response to an external address signal and write-in data, and at the same time, senses data that has been read out along global bit line GBL from a memory cell transistor which corresponds to the external address signal so as to transfer the data to an external I/O. X decoder XD selects a word line WL in response to an address signal that is supplied from the outside.
As shown in FIG. 33, each string ST includes a plurality of word lines WL (256 in the figure), and a plurality of memory cell transistors MC and a plurality of assist gate transistors AGT which are provided so as to correspond to each word line WL. Each memory cell transistor MC has a control gate and a floating gate, and stores information based on a level change of its threshold voltage. The control gate of each memory cell transistor MC is connected to a corresponding word line WL. A plurality of assist gate transistors AGT (256 in this case) which are arranged in a line in the direction crossing word lines WL have a channel length equal to the width of one string in the direction crossing word lines WL, in such a manner that assist gates AG, which are the gates thereof, also have a length corresponding to one string. In each row, those plurality of memory cell transistors MC are grouped into groups of four, and, those plurality of assist gate transistors AGT are also grouped into groups of four so as to correspond to this, as are assist gates AG. That is to say, each memory cell transistor group includes four memory cell transistors MC0 to MC3, each assist gate transistor group includes four assist gate transistors AGT0 to AGT3, and each assist gate group includes four assist gates AG0 to AG3.
Two global bit lines GBL are provided so as to correspond to each group made of four assist gates AG. In FIG. 33, four global bit lines GBL<2*m> (EVEN NUMBER), GBL<2*m+1> (ODD NUMBER), GBL<2*m+2> (EVEN NUMBER), and GBL<2*m+3> (ODD NUMBER) corresponding to two groups are shown. The lower layer of an assist gate AG0 is connected to a global bit line GBL<2*m> (here, m is an integer of no smaller than 0) via an N channel MOS transistor Q0. The lower layer of an assist gate AG2 is connected to a global bit line GBL<2*m+1> via an N channel MOS transistor Q2. The gates of N channel MOS transistors Q0 and Q2 both receive a signal STS.
The lower layer of an assist gate AG1 is connected to a common drain line CD via an N channel MOS transistor Q1. The lower layer of an assist gate AG3 is connected to common drain line CD via an N channel MOS transistor Q3. The gates of N channel MOS transistors Q1 and Q3 both receive a signal STD. When a predetermined voltage is applied to an assist gate AG, an intense inversion layer is formed beneath this assist gate AG so as to become an inversion layer bit line BL.
Next, the read-out operation of this AG-AND type flash memory is described. FIG. 34 is a diagram showing the voltage of each signal at the time of the read-out operation, and FIG. 35 is a time chart showing the waveform of each signal during operation. Here, it is assumed that data that has been stored in a memory cell transistor MC2 in each memory cell transistor group corresponding to first word line WL0 is read out.
In order to read out the data of memory cell transistor MC2 to global bit line GBL, predetermined voltages (both are 3.5 V in FIGS. 34 and 35) are supplied to assist gates AG1 and AG2, so that inversion layer bit lines BL are formed beneath assist gates AG1 and AG2. As a result of this, inversion layer bit line BL beneath assist gate AG2 corresponding to the drain of memory cell transistor MC2 is connected to global bit line GBL of an odd number via transistor Q2 which receives signal STS. Meanwhile, inversion layer bit line BL beneath assist gate AG1 is connected to common drain line CD via transistor Q1 which receives signal STD, so as to function as the source of memory cell transistor MC2.
In FIG. 35, global bit line GBL of an odd number has been charged to 1.2 V in advance, and is triggered by the end of the rise of signal STD from level “L” to level “H,” so that the charge of global bit line GBL of an odd number is discharged to common drain line CD via memory cell transistor MC2 in the case where threshold voltage VTHC of memory cell transistor MC2 is lower than selection voltage VRW of word line WL0, and thus, the voltage of global bit line GBL of an odd number gradually lowers.
Conversely, in the case where threshold voltage VTHC of memory transistor MC2 is higher than selection voltage VRW of word line WL0, memory cell transistor MC2 is not turned on, and thus, the voltage of global bit line GBL of an odd number stays at 1.2 V. After an appropriate amount of time, for example, the time required for the voltage of global bit line GBL of an odd number to swing to 0.6 V when VRW>VTHC, has passed, a signal SENSE in FIG. 35 becomes of level “H,” and data is finally latched to the sense amplifier within sense latch SL in accordance with the voltage of global bit line GBL of an odd number at this point in time.
Next, the write-in operation of this AG-AND type flash memory is described. In a multiple value memory cell transistor MC where data of two or more bits is made to correspond to one memory cell transistor MC, it is necessary to raise threshold voltage VTHC so that the memory cell transistor is changed to any of a plurality of write-in states from the erased state, which has the lowest threshold voltage VTHC. At this time, the amount of shift in threshold voltage VTHC, that is to say, the amount of charge to be injected into a floating gate FG, differs depending on which write-in state is selected. Therefore, it becomes possible to use different write-in operations on the basis of the amount of shift in threshold voltage VTHC.
FIG. 36 is a diagram showing the relationship between the potential of each signal within object string ST at the time of write-in operation according to the conventional art, and FIG. 37 is a time chart showing the waveform of each signal during operation. Memory cell transistor MC2 in each memory cell transistor group is assumed to be the object of write-in. In addition, the “cell through write-in system” disclosed in the above described Non-Patent Document 1 is used.
In FIG. 36, inversion layer bit line BL beneath assist gate AG2 functions as the drain of memory cell transistor MC2, and inversion layer bit line BL beneath assist gate AG0 functions as the source of memory cell transistor MC2. 4.5 V is supplied to inversion layer bit line BL on the drain side from global bit line GBL of an odd number via transistor Q2, and 0 V or approximately 2 V is supplied to inversion layer bit line BL on the source side from global bit line GBL of an even number via transistor Q0. The voltage of inversion layer bit line BL on this source side reflects information on whether or not write-in is carried out on memory cell transistor MC2, and is based on the data that is stored in sense latch SL. Concretely, in the case where write-in is desired, inversion layer bit line BL on the source side is set to 0 V, and in the case where write-in is desired to be blocked, inversion layer bit line BL on the source side is set to approximately 2 V. Such a system, where it is determined on the basis of the voltage that is supplied to inversion layer bit line BL on the source side whether or not write-in is carried out on memory cell transistor MC, is hereinafter referred to as source selection write-in system.
With reference to FIG. 37, the voltage that is applied to assist gate AG1 triggers initiation of write-in into memory cell transistor MC2. At this time, the voltage that is applied to assist gate AG1 is as low as approximately 1 V, and the inversion layer that is formed beneath assist gate AG1 is in a state of weak inversion. In the case where inversion layer bit line BL on the source side is 0 V, a current flows from global bit line GBL on the odd number side to global bit line GBL on the even number side through the portion beneath memory cell transistor MC1, and the electrical field becomes concentrated in the vicinity of the border between the channel beneath memory cell transistor MC2, which is the object of write-in, and the weak inversion layer beneath assist gate AG1, and electrons having a high level of energy (hot electrons) which have been accelerated by this electrical field occurs on the surface of the substrate. These hot electrons are drawn by the electrical field that has been created in the longitudinal direction by high voltage VWW that has been applied to word line WL, and reach the floating gate of memory cell transistor MC2 which is the object of write-in. This is referred to as source side hot electron injection (SSI). In the case where inversion layer bit line BL on the source side is at 2 V, voltage VAG1 which is supplied to assist gate AG1 is 1 V, and therefore, assist gate AG1 is cut off and no write-in current flows through memory cell transistor MC2. Here, the arrow along the current path in FIG. 36 shows the direction in which electrons flow.
Furthermore, global bit lines GBL on both the odd number side and the even number side are converted to a floating state at the time of write-in, and thereby, the charge that has been stored in global bit line GBL on the drain side flows into global bit line GBL on the source side, so that the charge is redistributed between the two until assist gate AG1 is cut off (charge sharing system). As a result, controllability of write-in (uniformity in amount of shift in threshold voltage VTHC between memory cell transistors MC) is increased, by maintaining the charge that is consumed for one write-in at a constant level.
Next, another write-in operation of this AG-AND type flash memory is described. FIG. 38 is a diagram showing the relationship between the potential of each signal within object string ST at the time of another write-in operation according to the conventional art, and FIG. 39 is a time chart showing the waveform of each signal during operation. Memory cell transistor MC2 in each memory cell transistor group is assumed to be the object of write-in.
In FIG. 38, the relationship between inversion layer bit lines BL on the source side and on the drain side, and assist gates AG is the same as in FIG. 36, and the source selection write-in system is used in the same manner. Here, the voltage that is supplied to inversion layer bit line BL on the drain side is supplied in accordance with the below described “self-boosting” system of FIG. 38, which is different from FIG. 36. With reference to the waveform during operation of FIG. 39, in the case where the voltage of assist gate AG2 is raised from 0 V to 8 V after signal STS is lowered from level “H” to level “L,” the voltage of inversion layer bit line BL beneath assist gate AG2 increases, due to capacitive coupling. The final voltage of inversion layer bit line BL beneath assist gate AG2 is determined by the ratio of the capacitance of the gate oxidation film beneath assist gate AG2 to the capacitance of the depletion layer in the intense inversion layer that is formed beneath assist gate AG2, and increases to, for example, 4.5 V.
When the voltage of assist gate AG1 is raised to 1 V, write-in is initiated. Signal STS stays at level “L,” and therefore, inversion layer bit lines BL on the source side and on the drain side are in a floating state, and write-in is carried out in a charge sharing system where the charge that has been stored in the two is redistributed.
As described above, as the write-in system, the source selection system according to which whether or not write-in is carried out is determined on the basis of the voltage on the source selection, the charge sharing system where controllability is enhanced by redistributing constant charge that has been stored in the source/drain in a floating state, and the self-boosting system, where the drain voltage is locally generated by boosting assist gate AG, are used together. In particular, charge sharing system includes a charge sharing system between global bit lines GBL and a charge sharing system between inversion layer bit lines BL, making it possible to select either for use on the basis of the amount of shift in the desired VTHC.
The amount of shift in VTHC in the charge sharing system depends on the amount of charge that is stored in the parasitic capacitance between wires, and for the same drain voltage, a greater VTHC shift can be expected in the charge sharing system between global bit lines GBL of which the parasitic capacitance between wires is as great as 0.8 pF than in the charge sharing system between inversion layer bit lines BL of which the parasitic capacitance between wires is as small as 0.02 pF. Meanwhile, in the case where VTHC of the bit that protrudes due to the reduction in the width of the VTHC distribution is microscopically adjusted, the charge sharing system between inversion layer bit lines BL is appropriate. In addition, the time for setup before write-in is shorter in the charge sharing system between inversion layer bit lines BL according to which inversion bit lines BL having a lighter load are self-boosted. Using these characteristics, optimization of the time for write-in can be achieved, particularly in the case where write-in is carried out at levels of multiple values.
The write-in system shown in FIG. 38, where the self-boosting system and the charge sharing system between inversion layer bit lines BL are used together is excellent in terms of controllability for write-in and time for setup. There is a possibility, however, that a problem as that described below may arise as the miniaturization of memory cell transistors MC progresses.
The gate width of assist gates AG is being scaled down together with the miniaturization of memory cell transistors MC. As a result, the ratio of fringe component (one type of linear component) which does not depend on the gate width of assist gate AG is increasing, from among the components of the capacitance of the depletion layer in the inversion layer that is formed beneath assist gate AG. Therefore, the surface component of the capacitance of the depletion layer and the gate capacitance both become smaller in proportion to the gate width of assist gate AG, while the entire capacitance of the depletion layer, including the fringe component, becomes smaller more gradually than the ratio of scaling down of the gate width. Accordingly, in order to secure the drain voltage after self-boosting at approximately the same level as in the conventional art, the voltage of assist gate AG needs to be increased, or the gate oxide film that forms assist gate AG needs to be reduced in thickness. Meanwhile, the drain voltage lowers after charge sharing (see FIG. 39), and in the case where a voltage higher than in the conventional art, or a gate oxide film which is thinner than that in the conventional art are used, as described above, the intensity of the electrical field that is applied to the assist gate oxide film after charge sharing becomes high, and thus, it is possible that a problem may arise with reliability.
In order to avoid such a problem, though it is possible to carry out write-in only in accordance with the charge sharing system between global bit lines GBL, as described above, the parasitic capacitance greatly differs between global bit lines GBL and inversion layer bit lines BL, which have 0.8 pF and 0.02 pF, respectively, and therefore, it seems to be difficult to create sufficiently small distribution in threshold voltage VTHC after write-in only in accordance with the charge sharing system between global bit lines GBL, because of the controllability of the amount of shift in VTHC. In addition, in accordance with the charge sharing system between global bit lines GBL, global bit lines GBL having a heavy load are charged and discharged for every write-in cycle, and therefore, the time for charging global bit lines GBL before write-in becomes long, making the time for write-in long, and there is a concern that power consumption may increase.
In addition, the time for write-in includes a verifying operation for determining excess and deficiency in the amount of shift in VTHC after write-in. This is a type of operation for reading out from memory cell transistor MC, and takes time in the case where large amplitude is induced in global bit lines GBL having a heavy load for read-out, as in the conventional art.